In a large number of applications requiring the processing of digital data at a high bit-rate, the transmission of the data between two processing units takes place via serial links, which allows the cabling to be reduced and the connection system between the various processing units to be simplified. In contrast, the processing of the data is performed in parallel by the processing units for reasons of efficiency.
For parallel-serial and serial-parallel conversions, converters called serializers or deserializers are used, which convert the serial signals into parallel signals and vice versa. In general, the two functions are grouped in a single integrated circuit called a SERDES, an abbreviation for SERializer-DESerializer.
SERDES are used particularly for the transmission of digital video signals. Video signals are governed by definition and transmission standards. The main bodies generating these standards are the CCIR, ‘Comité Consultatif International des Radiocommunications’, and the SMPTE, Society of Motion Picture Television Engineers.
Certain standards such as the SMPTE 259, which is the serial transmission version of the video standard SMPTE 125, impose the strict  compliance with the synchronous nature of the transmission of the video signals. The signals are referred to as synchronous when the frequency of transmission of the signal is an exact multiple of the pixel frequency, which is itself an exact multiple of the line frequency, which is an exact multiple of the frame frequency or field rate. This obligation leads to significant hardware complications for the electronic units having to receive or to transmit such signals such as, for example, switching units. One reason is that the transmission of synchronous signals implies that the clock of the deserializer has a frequency perfectly identical to that of the video signal. In order to resolve this difficulty, there exist two major types of solution.
The first type of solution is illustrated in FIG. 1 that shows an electronic assembly successively comprising 5 main elements:                A first link 101 for transmission of high bit-rate serial digital video signals;        A deserializer 102 conventionally included in a first SERDES component 104 which transforms the serial input signal into parallel signals;        An electronic unit 105 for processing the parallel signals;        A serializer 103 conventionally included in a second SERDES component 104 which transforms the parallel signals into a serial output signal;        A second link 107 for transmission of high bit-rate serial digital video signals.        
In this figure and in the following two, the following conventions have been adopted:                The serial signals are represented by black-line arrows;        The parallel signals are represented by wide outline arrows.        
In this type of configuration, an analog phase-loop clock recovery circuit is used that is included in the first SERDES component which is only used in receiver mode. It uses a fixed-frequency oscillator as reference clock. Its analog phase-loop clock recovery circuit delivers a clock signal synchronous with the source at the pixel frequency. All the upstream circuits cooperating in the regeneration of an SDI output depending on the input signal then use this clock signal. If this clock possesses too much jitter, an additional phase loop may be inserted that has a very low cutoff frequency  and a high quality oscillator of the VCXO type, acronym for Voltage Controlled Crystal Oscillator. This option is illustrated in FIG. 1 where the oscillator 108 is represented by a dashed-line rectangle. The serializer of the first SERDES used in receiver mode cannot be used in transmission mode since its internal clock is not synchronous with the frequency of the input signal. As illustrated in FIG. 1, a second SERDES must therefore be used for the serialization of the serial output signal.
This solution has the drawback of requiring specific SERDES components capable of operating with the “pathological patterns” of the SMPTE 259 standard. “Pathological patterns” is taken to mean any long succession of the same logic state; for example, a succession of 20 “0”s. Said succession is generally called “run length”.
The manufacturers of components of the FPGA type, acronym for Field Programmable Gate Array, offer very high bit-rate SERDES components, designed for bit-rates equal to or greater than 622 Mbauds. Their analog phase-loop clock recovery circuits are not compatible with lower bit-rate applications.
At lower bit-rate, the specific SERDES components have the drawbacks of not being able to be integrated into components of the FPGA type and of having a high power consumption and a large space requirement.
The second type of solution is illustrated in FIG. 2 which shows an electronic assembly comprising 5 main elements:                A first link 101 for transmission of high bit-rate serial digital video signals;        A second link for transmission 107 of high bit-rate serial digital video signals;        A single SERDES component 104 comprising:                    a deserializer 102 which transforms the serial input signal into parallel input signals and            a serializer 103 which transforms the parallel output signals into a serial output signal;                        An electronic processing unit 105 for the parallel signals;        A frame frequency converter 109 also known as a Field Rate Converter.        
The principle of operation consists in completely regenerating an  SDI video signal by means of a field rate converter 109. This converter uses frame buffers 110 according to modes which can be either “triple page” or FIFO, acronym for “First In-First Out”. The circuits upstream of this converter use a clock signal generated in the equipment and all the pixel, line and field frequencies of the output signal are exact divisions of the frequency of this clock signal. Thus, the perfectly synchronous nature of the output signal is complied with. This second solution is costly and complex as regards the hardware. The storage in frame buffers necessarily adds a latency time corresponding to the duration of two frames or two images within the transmission chain. This latency time can prove to be unacceptable when the video information is to be used in real time.
The company ALTERA offers a solution allowing this problem of synchronization of the clock to be solved. This solution is based on the principle of asynchronous over-sampling. The clock for the deserializer is locked onto its reference frequency input instead of being locked onto the frequency of the input signal.
The latter is over-sampled generally with a nominal ratio of 5. For example, if the bit-rate of the input signal is equal to 270 Mbauds, the deserializer operates with a sampling frequency of 1350 Mbauds. The deserialization can be carried out, for example, over 10 bits of the input signal. Consequently, if the over-sampling is in a ratio of 5, for each parallel word of 10 bits, on average 2 samples of the signal are extracted. However, since the reference frequency of the deserializer is produced by an oscillator that is not synchronous, a phase slip will occur that requires either a single sample or three samples to be periodically captured, depending on the sign of frequency difference. The samples are stored in a buffer register from which a word of fixed width is extracted. The rhythm at which the 10 samples are acquired is therefore equal to 27 megahertz. In order to decode the video signal, it just remains to carry out the conventional functions for this type of transmission:                decode the bus according to the pseudo-random code of the standard, an operation called “descrambling”;        recognize the video synchronization messages;        recover the phase of the words, an operation called “word boundaries synchronization”.         
This solution allows a large number of interfaces to be integrated into a single circuit while at the same time conserving a low electrical power consumption, but the frequencies of the input signal are lost. The frequency of the recovered signal is indeed, on average, 27 megahertz. However, with respect to the clock signal of 135 megahertz synchronous with the clock frequency of the deserializer, although the period of the signal is very often equal to the duration of 5 samples, it may occasionally also be equal to 4 or 6 sample times. As a result, the jitter introduced is too large to retransmit a synchronous signal. It is possible to introduce a phase loop in order to filter the frequency of the output signals and restore a perfectly regular clock, but the electronic design of this phase loop proves to be particularly arduous.
The techniques of analog phase loop clock recovery and of over-sampling are usually contradictory; the first is used for high bit-rates, close to the speed limits of the components, and the second is used for low bit-rates.